View M29F800FB55N3E2_7786517.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

micron parallel nor flash embedded memory top/bottom boot block 5v supply m29f200ft/b, m29f400ft/b, m29f800ft/b, m29f160ft/b features ? supply voltage C v cc = 5v ? access time: 55ns ? program/erase controller C embedded byte/word program algorithms ? erase suspend and resume modes ? low power consumption C standby and automatic standby ? 100,000 program/erase cycles per block ? electronic signature C manufacturer code: 0x01h ? top device codes C m29f200ft: 0x2251 C m29f400ft: 0x2223 C m29f800ft: 0x22d6 C m29f160ft: 0x22d2 ? bottom device codes C m29f200fb: 0x2257 C m29f400fb: 0x22ab C m29f800fb: 0x2258 C m29f160fb: 0x22d8 ? rohs-compliant packages C tsop48 C so44 (16mb not available for this package) ? automotive device grade 3 C temperature: C40 to +125c ? automotive device grade 6 C temperature: C40 to +85c ? automotive grade certified (aec-q100) m29fxxxft/b features pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
part numbering information devices are shipped from the factory with memory content bits erased to 1. for available options, such as pack- ages, or for further information, contact your micron sales representative. part numbers can be verified at www.micron.com . feature and specification comparison by device type is available at www.micron.com/products . contact the factory for devices not found. table 1: part number information part number category category details device type m29f = 5v density 200 = 2mb 400 = 4mb 800 = 8mb 160 = 16mb (not available in so 44 package) technology f = 110nm configuration t = top boot b = bottom boot speed 55 = 55ns device speed in conjunction with temperature range = 3, which denotes auto grade C 40 to 125 c parts 5a = 55ns access time (auto grade) only in conjunction with the grade 6 option package m = so 44 n = tsop 48 12mm x 20mm al 42 temperature range 6 = C40c to +85c 3 = C40c to +125c shipping options blank = standard packing (tray) e = rohs-compliant package, standard packing (tray) t = tape and reel packing (24mm) f = rohs-compliant package, tape and reel packing (24mm) fab location 2 = fab 13 (singapore) m29fxxxft/b features pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
contents general description ......................................................................................................................................... 6 signal assignments ......................................................................................................................................... 15 tsop pin assignments ................................................................................................................................ 15 small-outline pin assignments ................................................................................................................... 19 signal descriptions ......................................................................................................................................... 22 bus operations ............................................................................................................................................... 24 read .......................................................................................................................................................... 24 write .......................................................................................................................................................... 24 output disable ........................................................................................................................................... 24 standby ..................................................................................................................................................... 24 automatic standby ..................................................................................................................................... 24 command interface ....................................................................................................................................... 25 read/reset command ............................................................................................................................ 25 auto select command ........................................................................................................................... 25 program command ................................................................................................................................ 26 unlock bypass command ...................................................................................................................... 26 unlock bypass program command ..................................................................................................... 27 unlock bypass reset command ............................................................................................................ 27 chip erase command .............................................................................................................................. 27 block erase command ........................................................................................................................... 27 erase suspend command ....................................................................................................................... 28 erase resume command ........................................................................................................................ 28 read cfi query command ...................................................................................................................... 28 16-bit mode commands ......................................................................................................................... 29 8-bit mode commands ........................................................................................................................... 30 block protection operations ........................................................................................................................... 31 programmer technique .............................................................................................................................. 32 in-system technique .................................................................................................................................. 34 status register ................................................................................................................................................ 36 data polling bit .......................................................................................................................................... 36 toggle bit ................................................................................................................................................... 37 error bit ..................................................................................................................................................... 38 erase timer bit ........................................................................................................................................... 38 alternative toggle bit .................................................................................................................................. 39 common flash interface (cfi) ........................................................................................................................ 40 maximum ratings and operating conditions .................................................................................................. 44 dc electrical specifications ............................................................................................................................ 46 ac read characteristics .................................................................................................................................. 47 ac write characteristics ................................................................................................................................. 49 reset specifications ........................................................................................................................................ 51 program/erase characteristics .................................................................................................................. 52 package dimensions ....................................................................................................................................... 53 revision history ............................................................................................................................................. 55 rev. b C 2/14 ............................................................................................................................................... 55 rev. a C 2/13 ............................................................................................................................................... 55 m29fxxxft/b features pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
list of figures figure 1: logic diagram ................................................................................................................................... 6 figure 2: block addresses, m29f160 (x8) .......................................................................................................... 7 figure 3: block addresses, m29f160 (x16) ......................................................................................................... 8 figure 4: block addresses, m29f800 (x8) .......................................................................................................... 9 figure 5: block addresses, m29f800 (x16) ....................................................................................................... 10 figure 6: block addresses, m29f400 (x8) ........................................................................................................ 11 figure 7: block addresses, m29f400 (x16) ....................................................................................................... 12 figure 8: block addresses, m29f200 (x8) ........................................................................................................ 13 figure 9: block addresses, m29f200 (x16) ....................................................................................................... 14 figure 10: m29f160f ..................................................................................................................................... 15 figure 11: m29f800f ..................................................................................................................................... 16 figure 12: m29f400f ..................................................................................................................................... 17 figure 13: m29f200f ..................................................................................................................................... 18 figure 14: m29f800 ....................................................................................................................................... 19 figure 15: m29f400 ....................................................................................................................................... 20 figure 16: m29f200 ....................................................................................................................................... 21 figure 17: block protect flowchart C programmer equipment ......................................................................... 32 figure 18: chip unprotect flowchart C programmer equipment ..................................................................... 33 figure 19: block protect flowchart C in-system equipment ............................................................................. 34 figure 20: chip protection flowchart C in-system equipment ......................................................................... 35 figure 21: data polling flowchart ................................................................................................................... 37 figure 22: data toggle flowchart ................................................................................................................... 38 figure 23: ac measurement i/o waveform ..................................................................................................... 44 figure 24: ac measurement load circuit ....................................................................................................... 45 figure 25: read mode ac waveforms ............................................................................................................. 47 figure 26: write ac waveforms, write enable controlled ................................................................................ 49 figure 27: write ac waveforms, chip enable controlled ................................................................................. 50 figure 28: reset/block temporary unprotect ac waveforms ........................................................................... 51 figure 29: 48-lead tsop C 12mm x 20mm ...................................................................................................... 53 figure 30: 44-lead small-outline C 500 mil ..................................................................................................... 54 m29fxxxft/b features pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
list of tables table 1: part number information ................................................................................................................... 2 table 2: signal descriptions ........................................................................................................................... 22 table 3: bus operations ................................................................................................................................. 24 table 4: read electronic signature ................................................................................................................. 26 table 5: 16-bit mode commands (byte# = high) .......................................................................................... 29 table 6: 8-bit mode commands (byte# = low) ............................................................................................. 30 table 7: block and chip protection signal settings .......................................................................................... 31 table 8: status register bits ........................................................................................................................... 36 table 9: query structure overview ................................................................................................................. 40 table 10: cfi query identification string ........................................................................................................ 40 table 11: cfi query system interface information .......................................................................................... 41 table 12: device geometry definition ............................................................................................................ 41 table 13: primary algorithm-specific extended query table ........................................................................... 42 table 14: security code area .......................................................................................................................... 43 table 15: absolute maximum ratings ............................................................................................................. 44 table 16: operating and ac measurement conditions .................................................................................... 44 table 17: device capacitance ........................................................................................................................ 45 table 18: dc characteristics .......................................................................................................................... 46 table 19: read ac characteristics .................................................................................................................. 47 table 20: write ac characteristics, write enable controlled ............................................................................ 49 table 21: write ac characteristics, chip enable controlled ............................................................................. 50 table 22: reset/block temporary unprotect ac characteristics ...................................................................... 51 table 23: program/erase characteristics ........................................................................................................ 52 m29fxxxft/b features pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
general description this description applies specifically to the m29f 16mb (2 meg x 8 or 1 meg x 16) nonvo- latile memory device, but also applies to lower densities. the device enables read, erase, and program operations using a single, low-voltage (4.5C5.5v) supply. on power-up, the device defaults to read mode and can be read in the same way as a rom or eprom. the device is divided into blocks that can be erased independently, preserving valid da- ta while old data is erased. each block can be protected independently to prevent acci- dental program or erase operations from modifying the memory. program and erase commands are written to the command interface. an on-chip program/erase controller simplifies the process of programming or erasing the device by managing the operations required to update the memory contents. the end of a program or erase operation can be detected and any error conditions identified. the command set required to control the memory is consistent with jedec standards. the blocks are asymmetrically arranged. the first or last 64kb have been divided into four additional blocks. the 16kb boot block can be used for small initialization code to start the microprocessor. the two 8kb parameter blocks can be used for parameter storage. the remaining 32kb is a small main block where the application may be stored. ce#, oe#, and we# control the bus operation of the memory. they enable simple con- nection to most microprocessors, often without additional logic. devices are offered in 48-pin tsop (12mm x 20mm) and 44-pin small-outline packages. the device is sup- plied with all the bits erased (set to 1). figure 1: logic diagram 20 a[19:0] we# dq[7:0] dq[14:8] v cc ce# v ss 15 oe# rst# dq15/aC1 ry/by# byte# m29fxxxft/b general description pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 2: block addresses, m29f160 (x8) 1fffffh 1fc000h 01ffffh 010000h 00ffffh 000000h 1f7fffh 1f0000h 1e0000h 1effffh total of 31 64 kb blocks 1fffffh 1f0000h 003fffh 000000h 1effffh 01ffffh 1e0000h 010000h total of 31 64 kb blocks 00ffffh 008000h 1fbfffh 1fa000h 1f9fffh 1f8000h 007fffh 006000h 005fffh 004000h 16kb 64kb 64kb top boot block addresses (x8) 32kb 64kb 16kb 64kb 64kb bottom boot block addresses (x8) 32kb 64kb 8kb 8kb 8kb 8kb m29fxxxft/b general description pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 3: block addresses, m29f160 (x16) fffffh fe000h 0ffffh 08000h 07fffh 00000h fbfffh f8000h f0000h f7fffh total of 31 32 kword blocks fffffh f8000h 01fffh 00000h f7fffh 0ffffh f0000h 08000h total of 31 32 kword blocks 07fffh 04000h fdfffh fd000h fcfffh fc000h 03fffh 03000h 02fffh 02000h 8 kword 32 kword 32 kword 16 kword 32 kword 8 kword 32 kword 32 kword 16 kword 32 kword 4 kword 4 kword 4 kword 4 kword top boot block addresses (x16) bottom boot block addresses (x16) m29fxxxft/b general description pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 4: block addresses, m29f800 (x8) 16 kbyte fffffh fc000h 64 kbyte 1ffffh 10000h 64 kbyte 0ffffh 00000h top boot block addresses (x8) 32 kbyte f7fffh f0000h 64 kbyte e0000h effffh total of 15 64 kbyte blocks 16 kbyte fffffh f0000h 64 kbyte 64 kbyte 03fffh 00000h bottom boot block addresses (x8) 32 kbyte effffh 1ffffh 64 kbyte e0000h 10000h total of 15 64 kbyte blocks 0ffffh 08000h 8 kbyte 8 kbyte fbfffh fa000h f9fffh f8000h 8 kbyte 8 kbyte 07fffh 06000h 05fffh 04000h m29fxxxft/b general description pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 5: block addresses, m29f800 (x16) 8 kword 7ffffh 7e000h 32 kword 0ffffh 08000h 32 kword 07fffh 00000h 16 kword 7bfffh 78000h 32 kword 70000h 77fffh total of 15 32 kword blocks 8 kword 7ffffh 78000h 32 kword 32 kword 01fffh 00000h 16 kword 77fffh 0ffffh 32 kword 70000h 08000h total of 15 32 kword blocks 07fffh 04000h 4 kword 4 kword 7dfffh 7d000h 7cfffh 7c000h 4 kword 4 kword 03fffh 03000h 02fffh 02000h top boot block addresses (x16) bottom boot block addresses (x16) m29fxxxft/b general description pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 6: block addresses, m29f400 (x8) 7ffffh 7c000h 1ffffh 10000h 0ffffh 00000h 77fffh 70000h 60000h 6ffffh total of 7 64kb blocks 7ffffh 70000h 03fffh 00000h 6ffffh 1ffffh 60000h 10000h total of 7 64kb blocks 0ffffh 08000h fbfffh 7a000h 79fffh 78000h 07fffh 06000h 05fffh 04000h 16kb 64kb 64kb top boot block addresses (x8) 32kb 64kb 16kb 64kb 64kb bottom boot block addresses (x8) 32kb 64kb 8kb 8kb 8kb 8kb m29fxxxft/b general description pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 7: block addresses, m29f400 (x16) 3ffffh 3e000h 0ffffh 08000h 07fffh 00000h 3bfffh 38000h 30000h 37fffh total of 7 32 kword blocks 3ffffh 38000h 01fffh 00000h 37fffh 0ffffh 30000h 08000h total of 7 32 kword blocks 07fffh 04000h 3dfffh 3d000h 3cfffh 3c000h 03fffh 03000h 02fffh 02000h 8 kword 32 kword 32 kword top boot block addresses (x16) 16 kword 32 kword 8 kword 32 kword 32 kword bottom boot block addresses (x16) 16 kword 32 kword 4 kword 4 kword 4 kword 4 kword m29fxxxft/b general description pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 8: block addresses, m29f200 (x8) 16kb 3ffffh 3c000h 64kb 1ffffh 10000h 64kb 0ffffh 00000h top boot block addresses (x8) 32kb 37fffh 30000h 64kb 20000h 3ffffh total of 3 64kb blocks 16kb 2ffffh 20000h 64kb 64kb 03fffh 00000h bottom boot block addresses (x8) 32kb 2ffffh 1ffffh 64kb 20000h 10000h total of 3 64kb blocks 0ffffh 08000h 8kb 8kb 3bfffh 3a000h 39fffh 38000h 8kb 8kb 07fffh 06000h 05fffh 04000h m29fxxxft/b general description pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 9: block addresses, m29f200 (x16) 8 kword 1ffffh 1e000h 32 kword 0ffffh 08000h 32 kword 07fffh 00000h top boot block addresses (x16) 16 kword 3bfffh 18000h 32 kword 10000h 17fffh total of 3 32 kword blocks 8 kword 1ffffh 18000h 32 kword 32 kword 01fffh 00000h bottom boot block addresses (x16) 16 kword 17fffh 0ffffh 32 kword 10000h 08000h total of 3 32 kword blocks 07fffh 04000h 4 kword 4 kword 1dfffh 1d000h 3cfffh 1c000h 4 kword 4 kword 03fffh 03000h 02fffh 02000h m29fxxxft/b general description pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
signal assignments tsop pin assignments figure 10: m29f160f dq3 dq9 dq2 a6 dq0 we# a3 r/b# dq6 a8 a9 dq13 a17 a10 dq14 a2 dq12 dq10 dq15aC1 v cc dq4 dq5 a7 dq7 nc nc ai06850_160 12 1 13 24 25 36 37 48 dq8 nc a19 a1 a18 a4 a5 dq1 dq11 oe# a12 a13 a16 a11 byte# a15 a14 v ss ce# a0 rp# v ss m29fxxxft/b signal assignments pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 11: m29f800f dq3 dq9 dq2 a6 dq0 we# a3 r/b# dq6 a8 a9 dq13 a17 a10 dq14 a2 dq12 dq10 dq15aC1 v cc dq4 dq5 a7 dq7 nc nc ai06850_800 12 1 13 24 25 36 37 48 dq8 nc a1 a18 a4 a5 dq1 dq11 oe# a12 a13 a16 a11 byte# a15 a14 v ss ce# a0 rp# v ss nc m29fxxxft/b signal assignments pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 12: m29f400f dq3 dq9 dq2 a6 dq0 we# a3 r/b# dq6 a8 a9 dq13 a17 a10 dq14 a2 dq12 dq10 dq15aC1 v cc dq4 dq5 a7 dq7 nc nc ai06850_400 12 1 13 24 25 36 37 48 dq8 nc a1 a4 a5 dq1 dq11 oe# a12 a13 a16 a11 byte# a15 a14 v ss ce# a0 rp# v ss nc nc m29fxxxft/b signal assignments pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 13: m29f200f dq3 dq9 dq2 a6 dq0 we# a3 r/b# dq6 a8 a9 dq13 a10 dq14 a2 dq12 dq10 dq15aC1 v cc dq4 dq5 a7 dq7 nc nc ai06850_400 12 1 13 24 25 36 37 48 dq8 nc a1 a4 a5 dq1 dq11 oe# a12 a13 a16 a11 byte# a15 a14 v ss ce# a0 rp# v ss nc nc nc m29fxxxft/b signal assignments pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
small-outline pin assignments figure 14: m29f800 dq3 dq9 dq2 dq0 a8 a9 dq6 dq13 a17 dq12 dq10 dq15aC1 v cc dq4 dq5 dq14 dq7 ai02906_800 1 11 12 22 23 33 34 44 dq8 a6 a3 a2 a7 a1 a4 a5 dq1 dq11 oe# we# byte# a10 a16 a12 a13 a11 a15 a14 v ss a0 rp# r/b# v ss ce# a18 m29fxxxft/b signal assignments pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 15: m29f400 dq3 dq9 dq2 dq0 a8 a9 dq6 dq13 a17 dq12 dq10 dq15aC1 v cc dq4 dq5 dq14 dq7 ai02906_400 1 11 12 22 23 33 34 44 dq8 a6 a3 a2 a7 a1 a4 a5 dq1 dq11 oe# we# byte# a10 a16 a12 a13 a11 a15 a14 v ss a0 rp# r/b# v ss ce# nc m29fxxxft/b signal assignments pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 20 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 16: m29f200 dq3 dq9 dq2 dq0 a8 a9 dq6 dq13 dq12 dq10 dq15aC1 v cc dq4 dq5 dq14 dq7 ai02906_200 1 11 12 22 23 33 34 44 dq8 a6 a3 a2 a7 a1 a4 a5 dq1 dq11 oe# we# byte# a10 a16 a12 a13 a11 a15 a14 v ss a0 rp# r/b# v ss ce# nc nc m29fxxxft/b signal assignments pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 21 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
signal descriptions the signal description table below is a comprehensive list of signals for this device fami- ly. all signals listed may not be supported on this device. see signal assignments for in- formation specific to this device. table 2: signal descriptions name type description a[max:0] input address: selects the cells in the array to access during read operations. during write oper- ations, they control the commands sent to the command interface of the program/erase con- troller. ce# input chip enable: activates the device, enabling read and write operations to be performed. when ce# is high, all other pins are ignored. oe# input output enable: controls the bus read operation. we# input write enable: controls the bus write operation of the command interface. byte# input byte/word organization select: switches between x8 and x16 bus modes. when byte# is low, the device is in x8 mode; when high, the device is in x16 mode. rst# input reset: applies a hardware reset to the device, which is achieved by holding rst# low for at least t plpx. after rst# goes high, the device is ready for read and write operations (after t phel or t rhel, whichever occurs last). holding rst# at v id will temporarily unprotect the protected blocks. program and erase operations on all blocks will then be possible. the transition from v ih to v id must be slower than t phphh. dq[7:0] i/o data i/o: outputs the data stored at the selected address during a read operation. during write operations, they represent the commands sent to the command interface of the pro- gram/erase controller. dq[14:8] i/o data i/o: outputs the data stored at the selected address during a read operation when byte# is high. when byte# is low, these pins are not used and are high-z. during write operations, these bits are not used. when reading the status register, these bits should be ig- nored. dq15/a-1 i/o data i/o or address input: when the device operates in x16 bus mode, this pin behaves as data i/o, together with dq[14:8]. when the device operates in x8 bus mode, this pin behaves as the least significant bit of the address. except where stated explicitly otherwise, dq15 = data i/o (x16 mode); a-1 = address input (x8 mode). ry/by# output ready busy: open-drain output that can be used to identify when the device is performing a program or erase operation. during program or erase operations, ry/by# is low, and is high-z during read mode, auto select mode, and erase suspend mode. after a hard- ware reset, read and write operations cannot begin until ry/by# goes high-z (see reset ac specifications for more details). the use of an open-drain output enables the ry/by# pins from several devices to be connec- ted to a single pull-up resistor to v ccq . a low value will then indicate that one (or more) of the devices is (are) busy. m29fxxxft/b signal descriptions pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 22 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 2: signal descriptions (continued) name type description v cc supply supply voltage: provides the power supply for read, program, and erase operations. the command interface is disabled when v cc < v lko . this prevents write operations from accidentally damaging the data during power-up, power-down, and power surges. if the pro- gram/erase controller is programming or erasing during this time, then the operation aborts and the contents being altered will be invalid. a 0.1 f capacitor should be connected between v cc and v ss to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations (see dc characteristics). v ss supply ground: reference for all voltage measurements. all v ss pins must be connected to the sys- tem ground. nc C not connected: not connected internally. m29fxxxft/b signal descriptions pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 23 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
bus operations table 3: bus operations notes 1 through 2 apply to entire table operation ce# oe# we# 8-bit mode 16-bit mode a[max:0], dq15/a-1 dq[14:8] dq[7:0] a[max:0] dq15/a-1, dq[14:0] read l l h cell address high-z data output cell address data output write l h l command address high-z data input command address data input output disable x h h x high-z high-z x high-z standby h x x x high-z high-z x high-z notes: 1. h = logic level high (v ih ); l = logic level low (v il ); x = high or low. 2. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus operations. read bus read operations read from the memory cells or specific registers in the command interface. a valid bus read operation involves setting the desired address on the ad- dress inputs, taking ce# and oe# low, and holding we# high. the data i/os will out- put the value. (see ac characteristics for details about when the output becomes valid.) write bus write operations write to the command interface. a valid bus write operation begins by setting the desired address on the address inputs. the address inputs are latched by the command interface on the falling edge of ce# or we#, whichever occurs last. the data i/os are latched by the command interface on the rising edge of ce# or we#, whichever occurs first. oe# must remain high during the entire bus write oper- ation. (see ac characteristics for timing requirement details.) output disable data i/os are high-z when oe# is high. standby when ce# is high, the device enters standby, and data i/os are high-z. to reduce the supply current to the standby supply current (i cc2 ), ce# must be held within v cc 0.2v. (see dc characteristics.) during program or erase operations the device will contin- ue to use the program/erase supply current (i cc3 ) until the operation completes. automatic standby if cmos levels (v cc 0.2v) are used to drive the bus, and the bus is inactive for 150ns or more, the device enters automatic standby, and the internal supply current is reduced to that of the standby supply current, i cc2 . the data i/os will output data if a read op- eration is in progress. m29fxxxft/b bus operations pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 24 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
command interface all write operations are interpreted by the command interface. commands consist of one or more sequential write operations. failure to observe a valid sequence will re- sult in the memory returning to read mode. the long command sequences are imposed to maximize data security. the address used for the commands changes depending on whether the memory is in 16-bit or 8-bit mode. read/reset command the read/reset command returns the device to read mode, where it behaves like a rom or eprom, unless otherwise stated. it also resets the errors in the status register. either one or three write operations can be used to issue the read/reset command. the read/reset command can be issued, between write cycles, before the start of a program or erase operation, to return the device to read mode. once the program or erase operation has started, the read/reset command is no longer accepted. the read/reset command will not abort an erase operation when issued while in erase suspend. auto select command the auto select command is used to read the electronic signature, including the manufacturer code, the device code and the block protection status. three consecutive write operations are required to issue the auto select command. once the com- mand is issued, the memory remains in auto select mode until a read/reset com- mand is issued. read cfi query and read/reset commands are accepted in auto select mode, while all other commands are ignored. note: these operations are intended for use by programming equipment and are not typically used in applications. they require v id to be applied to some of the pins. from the auto select mode the manufacturer code can be read using a read operation with a0 = v il and a1 = v il . the other address bits may be set to either v il or v ih . the manufacturer code for micron is 0001h. the device code can be read using a read operation with a0 = v ih and a1 = v il . the other address bits may be set to either v il or v ih . the block protection status of each block can be read using a read operation with a0 = v il , a1 = v ih , and a12-a19 specifying the address of the block. the other address bits may be set to either v il or v ih . if the addressed block is protected then 01h is output on data inputs/outputs dq0-dq7, otherwise 00h is output. see block protection opera- tions for information on the block protection status; the programmer technique block protection table includes block protection bus read information. m29fxxxft/b command interface pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 25 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 4: read electronic signature notes 1 applies to entire table. operation ce# oe# we# 8-bit mode 16-bit mode a[max:0], dq15/a-1 dq[14:8] dq[7:0] a[max:0] dq15/a-1, dq[14:0] read manufacturer code l l h a0 = v il , a1 = v il , a9 = v id , others = v il /v id high-z 0x01 a0 = vil, a1 = vil, a9 = vid, others = vil/vid 0x0001 read device code l l h a0 = v ih , a1 = v il , a9 = v id , others = v il /v ih high-z 0x51 (m29f200ft) 0x57 (m29f200fb) 0x23 (m29f400ft) 0xab(m29f400fb) 0xd6 (m29f800ft) 0x58 (m29f800fb) 0xd2 (m29f160ft) 0xd8 (m29f160fb) a0 = vih, a1 = vil, a9 = vid, others = vil/vih 0x2251 (m29f200ft) 0x2257 (m29f200fb) 0x2223 (m29f400ft) 0x22ab (m29f400fb) 0x22d6 (m29f800ft) 0x2258 (m29f800fb) 0x22d2 (m29f160ft) 0x22d8(m29f160fb) note: 1. h = logic level high (v ih ); l = logic level low (v il ); x = high or low. program command the program command can be used to program a value to one address at a time. the command requires four bus write operations. the final write operation latches the address and data, and starts the program/erase controller. if the address falls in a protected block, then the program command is ignored, the data remains unchanged. the status register is never read and no error condition is giv- en. during the program operation, the memory will ignore all commands. it is not possi- ble to issue any command to abort or pause the operation. typical program times are given in read cfi query command. read operations during the program opera- tion will output the status register on the data i/os. (see registers.) after the program operation has completed, the memory returns to read mode, un- less an error has occurred. when an error occurs, the memory continues to output the status register. a read/reset command must be issued to reset the error condition and return to read mode. note that the program command cannot change a bit set at 0 back to 1. one of the erase commands must be used to set all the bits in a block, or in the whole device, from 0 to 1. unlock bypass command the unlock bypass command is used in conjunction with the unlock bypass program command to program the memory. when the access time to the device is long (as with some eprom programmers), considerable time saving can be made by using these commands. three write operations are required to issue the unlock by- pass command. m29fxxxft/b command interface pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 26 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
once the unlock bypass command has been issued, the memory will only accept the unlock bypass program command and the unlock bypass reset command. the memory can be read as though in read mode. unlock bypass program command the unlock bypass program command can be used to program one address in memory at a time. the command requires two write operations, the final write opera- tion latches the address and data, and starts the program/erase controller. the program operation using the unlock bypass program command behaves identically to the program operation using the program command. a protected block cannot be programmed; the operation cannot be aborted and the status register is read. errors must be reset using the read/reset command, which leaves the device in unlock bypass mode. (see the program command for details.) unlock bypass reset command the unlock bypass reset command can be used to return to read/reset mode from unlock bypass mode. two write operations are required to issue the unlock bypass reset command. the read/reset command does not exit from unlock bypass mode. chip erase command the chip erase command can be used to erase the entire chip. six write operations are required to issue the chip erase command and start the program/erase controller. if any blocks are protected then these are ignored and all the other blocks are erased. if all of the blocks are protected, the chip erase operation appears to start but will ter- minate within about 100s, leaving the data unchanged. no error condition is given when protected blocks are ignored. during an erase operation, the memory will ignore all commands. it is not possible to issue any command to abort the operation. typical chip erase times are given in read cfi query command. all read operations during the chip erase operation will out- put the status register on the data i/os. (see registers for more details.) after the chip erase operation has completed, the memory will return to read mode, unless an error has occurred. when an error occurs, the memory will continue to out- put the status register. a read/reset command must be issued to reset the error con- dition and return to read mode. the chip erase command sets all of the bits in unprotected blocks to 1. all previous data is lost. block erase command the block erase command can be used to erase a list of one or more blocks. six write operations are required to select the first block in the list. each additional block in the list can be selected by repeating the sixth write operation, using the address of the additional block. the block erase operation starts the program/erase controller about 50s after the last write operation. once the program/erase controller starts, it is not possible to select any more blocks. each additional block must therefore be selec- ted within 50s of the last block. the 50s timer restarts when an additional block is se- lected. the status register can be read after the sixth write operation. see status regis- m29fxxxft/b command interface pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 27 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
ter for details on how to identify whether the program/erase controller has started the block erase operation. if any selected blocks are protected, then these are ignored and all the other selected blocks are erased. if all of the selected blocks are protected, the block erase opera- tion appears to start but will terminate within about 100s, leaving the data unchanged. no error condition is given when protected blocks are ignored. during the block erase operation, the device will ignore all commands except the erase suspend command. all read operations during the block erase operation will output the status register on the data i/os. after the block erase operation has completed, the device will return to read mode, unless an error has occurred. when an error occurs, the device will continue to output the status register. a read/reset command must be issued to reset the error condi- tion and return to read mode. the block erase command sets all of the bits in the unprotected selected blocks to 1. all previous data in the selected blocks is lost. erase suspend command the erase suspend command may be used to temporarily suspend a block erase operation and return the device to read mode. the command requires one write oper- ation. the program/erase controller will suspend within the erase suspend latency time of the erase suspend command being issued. once the program/erase controller has stop- ped, the device will be set to read mode and the erase will be suspended. if the erase suspend command is issued during the period when the device is waiting for an addi- tional block (before the program/erase controller starts), then the erase is suspended immediately and will start immediately when the erase suspend command is issued. it is not possible to select any further blocks to erase after the erase resume. during erase suspend, it is possible to read and program cells in blocks that are not be- ing erased; both read and program operations behave as normal on these blocks. if any attempt is made to program in a protected block or in the suspended block then the program command is ignored and the data remains unchanged. the status register is not read and no error condition is given. reading from blocks that are being erased will output the status register. it is also possible to issue the auto select, read cfi query, and unlock bypass commands during an erase suspend. the read/reset command must be issued to re- turn the device to read array mode before the resume command will be accepted. erase resume command the erase resume command must be used to restart the program/erase controller from erase suspend. an erase can be suspended and resumed more than once. read cfi query command the read cfi query command reads data from the cfi. this command is valid when the device is in read array mode, or when the device is in auto select mode. one write cycle is required to issue the read cfi query command. once the command is issued, subsequent read operations then read from the cfi. the read/reset command m29fxxxft/b command interface pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 28 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
must be issued to return the device to the previous mode (read array or auto select mode). a second read/reset command would be needed if the device is to be placed in read array from auto select mode. 16-bit mode commands table 5: 16-bit mode commands (byte# = high) command length write operations 1st 2nd 3rd 4th 5th 6th addr data addr data addr data addr data addr data addr data read/reset 1 x f0 3 555 aa 2aa 55 x f0 auto select 3 555 aa 2aa 55 555 90 program 4 555 aa 2aa 55 555 a0 pa pd unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program 2 x a0 pa pd unlock bypass reset 2 x 90 x 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 block erase 6+ 555 aa 2aa 55 555 80 555 aa 2aa 55 ba 30 erase suspend 1 x b0 erase resume 1 x 30 read cfi query 1 55 98 notes: 1. x = "dont care;" pa = program address; pd = program data; ba = any address in the block. all values in the table are in hexadecimal. 2. command interface: only uses a-1, a[10;0], and dq[7;0] to verify the commands; a[19:11], dq[14:8], and dq15 are "dont care." dq15/a-1 is a-1 when byte is low or dq15 when byte is high. 3. read/reset: after a read/reset command, read the memory as normal until another command is issued. 4. auto select: after an auto select command, read manufacturer id, device id, or block protection status. 5. program, unlock bypass program, chip erase, block erase: after issuing these commands, read the status register until the program/erase controller completes and the device returns to read mode. add additional blocks during a block erase com- mand with additional bus write operations until the timeout bit is set. 6. unlock bypass: after the unlock bypass command, issue an unlock bypass pro- gram or unlock bypass reset command. 7. unlock bypass reset: after the unlock bypass reset command, read the memory as normal until another command is issued. 8. erase suspend: after the erase suspend command, read non-erasing blocks as nor- mal. issue auto select and program commands on non-erasing blocks as normal. 9. erase resume: after the erase resume command, the suspended erase operation re- sumes. read the status register until the program/erase controller completes and the de- vice returns to read mode. m29fxxxft/b command interface pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 29 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
10. cfi query: command is valid when device is ready to read array data or when device is in auto select mode. 8-bit mode commands table 6: 8-bit mode commands (byte# = low) command length write operations 1st 2nd 3rd 4th 5th 6th addr data addr data addr data addr data addr data addr data read/reset 1 x f0 3 aaa aa 555 55 x f0 auto select 3 aaa aa 555 55 aaa 90 program 4 aaa aa 555 55 aaa a0 pa pd unlock bypass 3 aaa aa 555 55 aaa 20 unlock bypass program 2 x a0 pa pd unlock bypass reset 2 x 90 x 00 chip erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 block erase 6+ aaa aa 555 55 aaa 80 aaa aa 555 55 ba 30 erase suspend 1 x b0 erase resume 1 x 30 read cfi query 1 aa 98 notes: 1. x = "dont care;" pa = program address; pd = program data; ba = any address in the block. all values in the table are in hexadecimal. 2. command interface: only uses a-1, a[10;0], and dq[7;0] to verify the commands; a[19:11], dq[14:8], and dq15 are "dont care." dq15/a-1 is a-1 when byte is low or dq15 when byte is high. 3. read/reset: after a read/reset command, read the memory as normal until another command is issued. 4. auto select: after an auto select command, read manufacturer id, device id, or block protection status. 5. program, unlock bypass program, chip erase, block erase: after issuing these commands, read the status register until the program/erase controller completes and the device returns to read mode. add additional blocks during a block erase com- mand with additional bus write operations until the timeout bit is set. 6. unlock bypass: after the unlock bypass command, issue an unlock bypass pro- gram or unlock bypass reset command. 7. unlock bypass reset: after the unlock bypass reset command, read the memory as normal until another command is issued. 8. erase suspend: after the erase suspend command, read non-erasing blocks as nor- mal. issue auto select and program commands on non-erasing blocks as normal. 9. erase resume: after the erase resume command, the suspended erase operation re- sumes. read the status register until the program/erase controller completes and the de- vice returns to read mode. 10. cfi query: command is valid when device is ready to read array data or when device is in auto select mode. m29fxxxft/b command interface pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 30 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
block protection operations block protection can be used to prevent any operation from modifying the data stored in the flash memory. each block can be protected individually. once protected, pro- gram and erase operations on the block fail to change the data. block protection status of the device is read using the auto select command. two techniques for controlling block protection are explained here: programmer tech- nique and in-system technique. note: a third technique for controlling block protection, temporary unprotection, is described in the signal descriptions table, rp pin (reset/block temporary unprotec- tion). unlike the command interface of the program/erase controller, the techniques for pro- tecting and unprotecting blocks could change between different flash memory suppli- ers. table 7: block and chip protection signal settings signals block protect chip unprotect verify block protec- tion verify block unpro- tect ce# l v id l l oe# v id v id l l we# l pulse l pulse h h address input, 8-bit and 16-bit a[max:16] block base address x block base address block base address a15 h a14 x a13 x a12 h a11 x x x x a10 x x x x a9 v id v id v id v id a8 x x x x a7 x x x x a6 x x l h a5 x x x x a4 x x x x a3 x x x x a2 x x x x a1 x x h h a0 x x l l data i/o, 8-bit and 16-bit m29fxxxft/b block protection operations pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 31 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 7: block and chip protection signal settings (continued) signals block protect chip unprotect verify block protec- tion verify block unpro- tect dq[15]/a-1, and dq[14:0] x x pass = xx01h retry = xx01h x x retry = xx00h pass = xx00h note: 1. h = logic level high (v ih ); l = logic level low (v il ); x = high or low. programmer technique the programmer technique uses high (v id ) voltage levels on some of the bus pins. these cannot be achieved using a standard microprocessor bus, therefore the techni- que is recommended only for use in programming equipment. to protect a block, follow the programmer equipment block protect flowchart. during the block protect algorithm, the a19-a12 address inputs indicate the address of the block to be protected. the block will be correctly protected only if a19-a12 remain valid and stable, and if chip enable is kept low, v il , all along the protect and verify phases. the chip unprotect algorithm is used to unprotect all the memory blocks at the same time. this algorithm can only be used if all of the blocks are protected first. to unprotect the chip follow the programmer equipment chip unprotect flowchart and the program- mer technique block protection table, which give a summary of each operation. the timing on these flowcharts is critical. care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. do not abort the procedure be- fore reaching the end. chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing. figure 17: block protect flowchart C programmer equipment verify protect setup end address = block address n = 0 start we# = v ih oe#, a9 = v id , ce# = v il wait 4s wait 100s we# = v il we# = v ih ce#, oe# = v ih , a0, a6 = v il , a1 = v ih data = 01h yes yes no ce# = v il wait 4s oe# = v il wait 60ns read data a9 = v ih ce#, oe# = v ih ++n = 25 fail pass a9 = v ih ce#, oe# = v ih no m29fxxxft/b block protection operations pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 32 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 18: chip unprotect flowchart C programmer equipment protect all blocks a6, a12, a15 = v ih ce#, oe#, a9 = v id data we# = v ih ce#, oe# = v ih address = current block address a0 = v il , a1, a6 = v ih wait 10ms = 00h increment current block n = 0 current block = 0 wait 4s we# = v il ++n = 1000 start yes yes no no last block yes no ce# = v il wait 4s oe# = v il wait 60ns read data fail pass verify unprotect set-up end a9 = v ih ce#, oe# = v ih a9 = v ih ce#, oe# = v ih m29fxxxft/b block protection operations pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 33 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
notes: 1. address inputs a[9:12] give the address of the block that is to be protected. it is impera- tive that they remain stable during the operation. 2. during the protect and verify phases of the algorithm, ce# must be kept low. in-system technique the in-system technique requires a high voltage level on the reset/blocks temporary unprotect pin, rp. this can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use af- ter the flash memory has been fitted to the system. to protect a block follow the in-system equipment block protect flowchart . to unpro- tect the whole chip it is necessary to protect all of the blocks first, then all the blocks can be unprotected at the same time. to unprotect the chip follow the in-system equip- ment chip unprotect flowchart. the timing on these flowcharts is critical. care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. do not allow the microprocessor to service interrupts that will upset the timing and do not abort the procedure before reaching the end. chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing. figure 19: block protect flowchart C in-system equipment no ih write 60h address = block address a0 = v il , a1 = v ih , a6 = v il wait 100s write 40h address = block address a0 = v il , a1 = v ih , a6 = v il wait 4s read data address = block address a0 = v il , a1 = v ih , a6 = v il verify protect n = 0 start rst# = v id write 60h address = block address a0 = v il , a1 = v ih , a6 = v il setup rst# = v ih ++n = 25 fail pass yes data = 01h yes no rst# = v issue read/reset command issue read/reset command end m29fxxxft/b block protection operations pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 34 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 20: chip protection flowchart C in-system equipment write 60h any address with a0 = v il , a1 = v ih , a6 = v ih n = 0 current block = 0 wait 10ms write 40h address = current block address a0 = v il , a1 = v ih , a6 = v ih rst# = v ih ++n = 1000 start fail pass yes no data = 00h yes no rst# = v ih wait 4s read data address = current block address a0 = v il , a1 = v ih , a6 = v ih rst# = v id issue read/reset command issue read/reset command protect all blocks increment current block last block yes no write 60h any address with a0 = v il , a1 = v ih , a6 = v ih verify unprotect set-up end m29fxxxft/b block protection operations pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 35 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
status register bus read operations from any address always read the status register during program and erase operations. it is also read during erase suspend when an address within a block being erased is accessed. table 8: status register bits operation address dq7 dq6 dq5 dq3 dq2 rb# program any address dq7# toggle 0 C C 0 program during erase suspend any address dq7# toggle 0 C C 0 program error any address dq7# toggle 1 C C 0 chip erase any address 0 toggle 0 1 toggle 0 block erase before time- out erasing block 0 toggle 0 0 toggle 0 non-erasing block 0 toggle 0 0 no toggle 0 block erase erasing block 0 toggle 0 1 toggle 0 non-erasing block 0 toggle 0 1 no toggle 0 erase suspend erasing block 1 no toggle 0 C toggle 1 non-erasing block data read as normal 1 erase error good block ad- dress 0 toggle 1 1 no toggle 0 faulty block ad- dress 0 toggle 1 1 toggle 0 note: 1. unspecified data bits should be ignored. data polling bit the data polling bit (dq7) can be used to identify whether the program/erase control- ler has successfully completed its operation or if it has responded to an erase suspend. the data polling bit is output on dq7 when the status register is read. during program operations the data polling bit outputs the complement of the bit be- ing programmed to dq7. after successful completion of the program operation the memory returns to read mode and bus read operations from the address just program- med output dq7, not its complement. during erase operations the data polling bit outputs 0, the complement of the erased state of dq7. after successful completion of the erase operation the memory returns to read mode. in erase suspend mode the data polling bit will output a 1 during a bus read opera- tion within a block being erased. the data polling bit will change from a 0 to a 1 when the program/erase controller has suspended the erase operation. the data polling flowchart, gives an example of how to use the data polling bit. a valid address is the address being programmed or an address within the block being erased. m29fxxxft/b status register pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 36 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 21: data polling flowchart read dq5 and dq7 at valid address start read dq7 at valid address fail pass ai03598 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no toggle bit the toggle bit (dq6) can be used to identify whether the program/erase controller has successfully completed its operation or if it has responded to an erase suspend. the toggle bit is output on dq6 when the status register is read. during program and erase operations the toggle bit changes from 0 to 1 to 0, etc., with successive bus read operations at any address. after successful completion of the operation the memory returns to read mode. during erase suspend mode the toggle bit will output when addressing a cell within a block being erased. the toggle bit will stop toggling when the program/erase controller has suspended the erase operation. if any attempt is made to erase a protected block, the operation is aborted, no error is signalled and dq6 toggles for approximately 100s. if any attempt is made to program a protected block or a suspended block, the operation is aborted, no error is signalled and dq6 toggles for approximately 1s. the data toggle flowchart, gives an example of how to use the data toggle bit. m29fxxxft/b status register pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 37 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 22: data toggle flowchart read dq6 start read dq6 twice fail pass ai01370c dq6 = toggle no no yes yes dq5 = 1 no yes dq6 = toggle read dq5 and dq6 error bit the error bit (dq5) can be used to identify errors detected by the program/erase con- troller. the error bit is set to 1 when a program, block erase or chip erase operation fails to write the correct data to the memory. if the error bit is set a read/reset com- mand must be issued before other commands are issued. the error bit is output on dq5 when the status register is read. note that the program command cannot change a bit set to 0 back to 1 and attempt- ing to do so will set dq5 to 1. a bus read operation to that address will show the bit is still 0. one of the erase commands must be used to set all the bits in a block or in the whole memory from 0 to 1 erase timer bit the erase timer bit (dq3) can be used to identify the start of program/erase controller operation during a block erase command. once the program/erase controller starts erasing the erase timer bit is set to 1. before the program/erase controller starts the erase timer bit is set to 0 and additional blocks to be erased may be written to the command interface. the erase timer bit is output on dq3 when the status register is read. m29fxxxft/b status register pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 38 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
alternative toggle bit the alternative toggle bit (dq2) can be used to monitor the program/erase controller during erase operations. the alternative toggle bit is output on dq2 when the status register is read. during chip erase and block erase operations the toggle bit changes from 0 to 1 to 0, etc., with successive bus read operations from addresses within the blocks being erased. a protected block is treated the same as a block not being erased. once the op- eration completes the memory returns to read mode. during erase suspend the alternative toggle bit changes from 0 to 1 to 0, etc. with successive bus read operations from addresses within the blocks being erased. bus read operations to addresses within blocks not being erased will output the memory cell data as if in read mode. after an erase operation that causes the error bit to be set the alternative toggle bit can be used to identify which block or blocks have caused the error. the alternative toggle bit changes from 0 to 1 to 0, etc. with successive bus read operations from address- es within blocks that have not erased correctly. the alternative toggle bit does not change if the addressed block has erased correctly. m29fxxxft/b status register pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 39 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
common flash interface (cfi) the common flash interface is a jedec approved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and func- tions supported by the memory. the system can interface easily with the device, ena- bling the software to upgrade itself when necessary. when the cfi query command is issued the device enters cfi query mode and the da- ta structure is read from the memory. addresses used to retrieve the data are shown in the following tables: the cfi data structure also contains a security area where a 64-bit unique security number is written. this area can be accessed only in read mode by the final user. it is impossible to change the security number after it has been written by micron. issue a read command to return to read mode. table 9: query structure overview address sub-section name description x16 x8 10h 20h cfi query identification string command set id and algorithm data offset 1bh 36h system interface information device timing & voltage information 27h 4eh device geometry definition flash device layout 40h 80h primary algorithm-specific extended query table additional information specific to the pri- mary algorithm (optional) 61h c2h security code area 64 bit unique device number note: 1. query data are always presented on the lowest order data outputs. table 10: cfi query identification string address data description value x16 x8 10h 20h 0051h "q" 11h 22h 0052h query unique ascii string "qry" "r" 12h 24h 0059h "y" 13h 26h 0002h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm amd compatible 14h 28h 0000h 15h 2ah 0040h address for primary algorithm extended query table (see the device geometry table.) p = 40h 16h 2ch 0000h 17h 2eh 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported na 18h 30h 0000h 19h 32h 0000h address for alternate algorithm extended query table na 1ah 34h 0000h note: 1. query data are always presented on the lowest order data outputs (dq7-dq0) only. dq8-dq15 are 0. m29fxxxft/b common flash interface (cfi) pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 40 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 11: cfi query system interface information address data description value x16 x8 1bh 36h 0045h v cc logic supply minimum program/erase voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 mv 4.5v 1ch 38h 0055h v cc logic supply maximum program/erase voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 mv 5.5v 1dh 3ah 0000h v pp [programming] supply minimum program/erase voltage na 1eh 3ch 0000h v pp [programming] supply maximum program/erase voltage na 1fh 3eh 0003h typical timeout per single byte/word program = 2 n s 8s 20h 40h 0000h typical timeout for minimum size write buffer program = 2 n s na 21h 42h 000ah typical timeout per individual block erase = 2 n ms 1 s 22h 44h 0000h typical timeout for full chip erase = 2 n ms na 23h 46h 0004h maximum timeout for byte/word program = 2 n times typical 256s 24h 48h 0000h maximum timeout for write buffer program = 2 n times typical na 25h 4ah 0003h maximum timeout per individual block erase = 2 n times typical 8 s 26h 4ch 0000h maximum timeout for chip erase = 2 n times typical na table 12: device geometry definition address data description value x16 x8 27h 4eh 0015h device size = 2 n in number of bytes 2mb 0014h 1mb 0013h 512kb 0012h 256kb 28h 29h 50h 52h 0002h 0000h flash device interface code description x8, x16 async. 2ah 2bh 54h 56h 0000h 0000h maximum number of bytes in multi-byte program or page = 2 n na 2ch 58h 0004h number of erase block regions within the device. it specifies the number of regions within the device containing contiguous erase blocks of the same size. 4 2dh 2eh 5ah 5ch 0000h 0000h region 1 information number of identical size erase block = 0000h+1 1 2fh 30h 5eh 60h 0040h 0000h region 1 information block size in region 1 = 0040h * 256 byte 16kb 31h 32h 62h 64h 0001h 0000h region 2 information number of identical size erase block = 0001h+1 2 33h 34h 66h 68h 0020h 0000h region 2 information block size in region 2 = 0020h * 256 byte 8kb m29fxxxft/b common flash interface (cfi) pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 41 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 12: device geometry definition (continued) address data description value x16 x8 35h 36h 6ah 6ch 0000h 0000h region 3 information number of identical size erase block = 0000h+1 1 37h 38h 6eh 70h 0080h 0000h region 3 information block size in region 3 = 0080h * 256 byte 32kb 39h 3ah 72h 74h 001eh 0000h region 4 information (2 mbyte) number of identical-size erase block = 001eh+1 31 39h 3ah 72h 74h 000eh 0000h region 4 information (1 mbyte) number of identical-size erase block = 000eh+1 15 39h 3ah 72h 74h 0006h 0000h region 4 information (512 kbyte) number of identical-size erase block = 0006h+1 7 39h 3ah 72h 74h 0002h 0000h region 4 information (256 kbyte) number of identical-size erase block = 0002h+1 3 3bh 3ch 76h 78h 0000h 0001h region 4 information block size in region 4 = 0100h * 256 byte 64kb table 13: primary algorithm-specific extended query table address data description value x16 x8 40h 80h 0050h primary algorithm extended query table unique ascii string pri "p" 41h 82h 0052h "r" 42h 84h 0049h "i" 43h 86h 0031h major version number, ascii "1" 44h 88h 0030h minor version number, ascii "0" 45h 8ah 0000h address sensitive unlock (bits 1 to 0) 00 = required, 01= not required silicon revision number (bits 7 to 2) yes 46h 8ch 0002h erase suspend 00 = not supported, 01 = read only, 02 = read and write 2 47h 8eh 0001h block protection 00 = not supported, x = number of blocks in per group 1 48h 90h 0001h temporary block unprotect 00 = not supported, 01 = supported yes 49h 92h 0002h 0004h 0008h 0160h block protect /unprotect 02 = m29f200 04 = m29f400 08 = m29f800 10 = m29f160 2 4 8 16 4ah 94h 0000h simultaneous operations, 00 = not supported no 4bh 96h 0000h burst mode, 00 = not supported, 01 = supported no m29fxxxft/b common flash interface (cfi) pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 42 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 13: primary algorithm-specific extended query table (continued) address data description value x16 x8 4ch 98h 0000h page mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word no table 14: security code area address data description x16 x8 61h c3h, c2h xxxx 64 bit: unique device number 62h c5h, c4h xxxx 63h c7h, c6h xxxx 64h c9h, c8h xxxx m29fxxxft/b common flash interface (cfi) pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 43 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
maximum ratings and operating conditions stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. table 15: absolute maximum ratings symbol parameter min max unit t bias temperature under bias C50 125 c t stg storage temperature C65 150 c v io input or output voltage C0.6 v cc +0.6 v v cc supply voltage C0.6 6 v v id identification voltage C0.6 13.5 v notes: 1. input or output voltage parameter: minimum voltage may undershoot to C2v during transition and for less than 20ns during transitions. 2. input or output voltage parameter: maximum voltage may overshoot to v cc +2v during transition and for less than 20ns during transitions. the parameters in the tables that follow, are derived from tests performed under the measurement conditions shown here. designers should check that the operating con- ditions in their circuit match the operating conditions when relying on the quoted pa- rameters. table 16: operating and ac measurement conditions parameter min max unit v cc supply voltage 4.5 5.5 v ambient operating temperature C40 125 c load capacitance (c l ) 30 30 pf input rise and fall times 5 ns input pulse voltages 0 to v cc 0 to v cc v input and output timing reference voltages v cc /2 v cc /2 v figure 23: ac measurement i/o waveform ai04498 v cc 0v v cc /2 m29fxxxft/b maximum ratings and operating conditions pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 44 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 24: ac measurement load circuit c l c l includes jig capacitance 25k w v cc 25k w v cc 0.1 f device under test table 17: device capacitance symbol parameter test condition min max unit c in input capacitance v in = 0v 6 pf c out output capacitance v out = 0v 12 pf note: 1. sampled only, not 100% tested. m29fxxxft/b maximum ratings and operating conditions pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 45 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
dc electrical specifications table 18: dc characteristics symbol parameter test condition min typ max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 supply current (read) ce# = v il , oe# = v ih , f = 6mhz 7 20 ma i cc2 supply current (standby) ce# = v cc 0.2v, rp# = v cc 0.2v 60 120 a i cc3 supply current (program/erase) program/erase controller active 30 ma v il input low voltage C C0.5 0.8 v v ih input high voltage C 0.7v cc v cc +0.3 v v ol output low voltage i ol = 1.8ma 0.45 v v oh output high voltage i oh = C100a v cc C0.4 v v id identification voltage 11.5 12.5 v i id identification current a9 = v id 100 a v lko program/erase lockout supply voltage C 1.8 2.3 v note: 1. supply current (program/erase) parameter: sampled only, not 100% tested. m29fxxxft/b dc electrical specifications pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 46 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
ac read characteristics figure 25: read mode ac waveforms t avav t avqv t axqx t elqx t ehqz t glqv t glqx t ghqx valid a[19:0]/ aC1 oe# dq[7:0]/ dq[15:8] ce# t elqv t ehqx t ghqz valid t bhqv t elbl/ t elbh t blqz byte# table 19: read ac characteristics symbol alt parameter test condition m29f160f unit 55/5a t avav t rc address valid to next address valid ce# = v il , oe# = v il min 55 ns t avqv t acc address valid to output valid ce# = v il , oe# = v il max 55 ns t elqx t lz chip enable low to output tran- sition oe# = v il min 0 ns t elqv t ce chip enable low to output valid oe# = v il max 55 ns t glqx t olz output enable low to output transition ce# = v il min 0 ns t glqv t oe output enable low to output valid ce# = v il max 20 ns t ehqz t hz chip enable high to output hi-z oe# = v il max 15 ns t ghqz t df output enable high to output hi-z ce# = v il max 15 ns t ehqx t ghqx t axqx t oh chip enable, output enable or address transition to output transition C min 0 ns m29fxxxft/b ac read characteristics pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 47 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 19: read ac characteristics (continued) symbol alt parameter test condition m29f160f unit 55/5a t elbl t elbh t elfl t elfh chip enable to byte# low or high C max 3 ns t blqz t flqz byte# low to output hi-z C max 15 ns t bhqv t fhqv byte# high to output valid C max 20 ns note: 1. t elqx t glqx t ehqz and t ghqz parameters: sampled only, not 100% tested. m29fxxxft/b ac read characteristics pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 48 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
ac write characteristics figure 26: write ac waveforms, write enable controlled ce# oe# we# a[19:0]/ aC1 dq[7:0]/ dq[15:8] v cc r/b# valid valid t vchel t wheh t whwl t elwl t avwl t whgl t wlax t whdx t avav t dvwh t wlwh t ghwl t whrl table 20: write ac characteristics, write enable controlled symbol alternate parameter m29f160f unit 55/5a t avav t wc address valid to next address valid min 55 ns t elwl t cs chip enable low to write enable low min 0 ns t wlwh t wp write enable low to write enable high min 30 ns t dvwh t ds input valid to write enable high min 20 ns t whdx t dh write enable high to input transition min 0 ns t wheh t ch write enable high to chip enable high min 0 ns t whwl t wph write enable high to write enable low min 15 ns t avwl t as address valid to write enable low min 0 ns t wlax t ah write enable low to address transition min 30 ns t ghwl output enable high to write enable low min 0 ns t whgl t oeh write enable high to output enable low min 0 ns t whrl t busy program/erase valid to rb# low max 20 ns m29fxxxft/b ac write characteristics pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 49 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 20: write ac characteristics, write enable controlled (continued) symbol alternate parameter m29f160f unit 55/5a t vchel t vcs v cc high to chip enable low min 50 s note: 1. t whrl parameter: sampled only, not 100% tested. figure 27: write ac waveforms, chip enable controlled valid valid t vchwl t ehwh t ehel t wlel t avel t ehgl t elax t ehdx t avav t dveh t eleh t ghel t ehrl ce# oe# we# a[19:0]/ aC1 dq[7:0]/ dq[15:8] v cc r/b# table 21: write ac characteristics, chip enable controlled symbol alt parameter m29f160f unit 55/5a t avav t wc address valid to next address valid min 55 ns t wlel t ws write enable low to chip enable low min 0 ns t eleh t cp chip enable low to chip enable high min 30 ns t dveh t ds input valid to chip enable high min 20 ns t ehdx t dh chip enable high to input transition min 0 ns t ehwh t wh chip enable high to write enable high min 0 ns m29fxxxft/b ac write characteristics pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 50 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 21: write ac characteristics, chip enable controlled (continued) symbol alt parameter m29f160f unit 55/5a t ehel t cph chip enable high to chip enable low min 15 ns t avel t as address valid to chip enable low min 0 ns t elax t ah chip enable low to address transition min 30 ns t ghel output enable high chip enable low min 0 ns t ehgl t oeh chip enable high to output enable low min 0 ns t ehrl t busy program/erase valid to rb# low max 20 ns t vchwl t vcs v cc high to write enable low min 50 s note: 1. t ehrl parameter: sampled only, not 100% tested. reset specifications figure 28: reset/block temporary unprotect ac waveforms r/b# we#, ce#, oe# rp# t plpx t phwl, t phel, t phgl t plyh t phphh t rhwl, t rhel, t rhgl table 22: reset/block temporary unprotect ac characteristics symbol alt parameter m29f160f unit 55/5a t phwl t phel t phgl t rh rp# high to write enable low, chip enable low, output enable low min 50 ns t rhwl t rhel t rhgl t rb rb# high to write enable low, chip enable low, output enable low min 0 ns t plpx t rp rp# pulse width min 500 ns t plyh t ready rp# low to read mode max 10 s t phphh t vidr rp# rise time to v id min 500 ns note: 1. t phwl t phgl t rhwl t rhel t rhgl t plyh and t phphh parameters: sampled only, not 100% tested. m29fxxxft/b reset specifications pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 51 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
program/erase characteristics table 23: program/erase characteristics parameter min typ max unit chip erase m29f160f 25 120 s m29f800f 12 60 m29f400f 6 30 m29f200f 3 15 block erase (64kb) 0.8 6 s erase suspend latency time 20 25 s program (byte or word) 11 200 s chip program (byte-by-byte) m29f160f 24 120 s m29f800f 12 60 m29f400f 6 30 m29f200f 4 16 chip program (word-by-word) m29f160f 12 60 s m29f800f 6 30 m29f400f 3 15 m29f200f 2 8 program/erase cycles (per block) 100,000 cycles data retention 20 years notes: 1. typical values are measured at room temperature and nominal voltages; typical and maximum values are samples, not 100% tested. 2. chip erase, program, and chip program parameters: maximum value measured at worst case conditions for both temperature and v cc after 100,000 program/erase cycles. 3. block erase and erase suspend latency parameter: maximum value measured at worst- case conditions for both temperature and v cc . m29fxxxft/b program/erase characteristics pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 52 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
package dimensions figure 29: 48-lead tsop C 12mm x 20mm die 1 24 48 25 0.50 typ 0.08 max 0.10 min/ 0.21 max 0.60 +0.10 + 3 o 2 o 3 o 0.22 +0.05 0.10 +0.05 1.20 max 1.00 +0.05 0.80 typ 20.00 +0.20 18.40 +0.10 12.00 +0.10 note: 1. drawing is not to scale. m29fxxxft/b package dimensions pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 53 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 30: 44-lead small-outline C 500 mil 44 1 22 23 8 0.35 min/ 0.50 max 0.18 min/ 0.28 max 0.10 typ 0.79 typ 1.73 typ 1.27 typ 0.10 max 28.50 0.13 12.60 0.13 16.03 +0.25 -0.26 2.69 +0.10 -0.13 3.00 max note: 1. drawing is not to scale. m29fxxxft/b package dimensions pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 54 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
revision history rev. b C 2/14 ? in block and chip protection section, added block protect and chip unprotect flow- charts rev. a C 2/13 ? initial micron brand release 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. m29fxxxft/b revision history pdf: 09005aef845656da m29fxxxf/t_2mb-16mb.pdf - rev. b 2/14 en 55 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.

▲Up To Search▲

Price & Availability of M29F800FB55N3E2

	To Download M29F800FB55N3E2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .